This application is a divisional of Serial No. 10/253,725; filed on Sep. 24, 2002 now U.S. Pat No. 7,059,049; which was Continuation-in-part application of Serial No. 10/067,551, filed Feb. 5, 2002, U.S. Pat. No. 6,829,823; which was a divisional application of Serial No. 09/540,172, filed Mar. 31, 2000, U.S. Pat. No. 6,373,717; which was a Continuation-in-part application of Serial No. 09/346,356, filed Jul. 2, 1999, U.S. Pat. No. 6,351,393.
1. Technical Field
The present invention relates, in general, to an electronic package for interconnecting a semiconductor chip to a printed circuit board, and in particular, to an organic multi-layered interconnect structure that includes dielectric layers whose ductility is controlled by a processes that laminates the dielectric layers to a thermally conductive layer within the multi-layered interconnect structure during fabrication.
2. Related Art
Organic substrates, such as chip carriers, have been and continue to be developed for many applications. Organic substrates are expected to displace ceramic substrates in many chip carrier applications because of reduced cost and enhanced electrical performance. An organic substrate, such as an organic chip carrier for interconnecting a semiconductor chip to a printed circuit board in an electronic package, may have a surface redistribution layer for redistributing electrical signals from the chip into a larger area so that the chip can properly interface with the printed circuit board.
As semiconductor chip input/output (I/O) counts increase beyond the capability of peripheral lead devices and as the need for both semiconductor chip and printed circuit board miniaturization increases, area array interconnects will be the preferred method for making large numbers of connections between a semiconductor chip and an organic chip carrier, and between the organic chip carrier and a printed circuit board. If the coefficient of thermal expansion (CTE) of the semiconductor chip, the organic chip carrier, and the printed circuit board are substantially different from one another, industry standard semiconductor chip array interconnections to the organic chip carrier may be subject to high stress during thermal cycling operation. Similarly, the industry standard ball grid array (BGA) interconnections between the organic chip carrier and printed circuit board may also be subject to high stress during operation. Significant reliability concerns may then become manifest by failure of the connections or even failure of the integrity of the semiconductor chip (chip cracking). These reliability concerns significantly inhibit design flexibility. For example, semiconductor chip sizes may be limited or interconnect sizes, shapes and spacing may have to be customized beyond industry standards to reduce these stresses. These limitations may limit the electrical performance advantages of the organic electronic package or add significant cost to the electronic package. Typically, a semiconductor chip has a CTE of 2-3 parts per million per degree Celsius (ppm/° C.) while a standard printed circuit board has a much greater CTE of 17-20 ppm/° C.
A particular reliability concern is that the surface redistribution layer, which interfaces between the organic substrate and the semiconductor chip, may be susceptible to stresses resulting from thermal cycling of the organic substrate together with a chip solderably coupled with the organic substrate. Such stresses result from a CTE differential between the surface redistribution layer and the remainder of the organic substrate. The ability of the surface redistribution layer to withstand such stresses depends on mechanical properties of the surface redistribution layer. If the redistribution layer cannot accommodate the thermal stresses, then the surface redistribution layer is susceptible to deterioration, such as cracking, which can cause failure of interconnections between the organic chip carrier and semiconductor chip, as well as between the organic chip carrier and printed circuit board. Thus, it is desirable for the surface redistribution layer to include a material having thermal and mechanical properties that enable the redistribution layer to reliably retain its structural integrity during thermal cycling operations.
Another reliability concern relates to the effect of mechanical properties of dielectric layers within the organic substrate on the ability of the organic substrate to withstand thermal stresses during thermal cycling of the organic substrate. Thus, it is desirable for dielectric layers within the organic substrate to have a mechanical property that promotes an improvement in thermal-cycling fatigue life of the organic substrate.